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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL,-85VLL, -70VXL,-85VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5256DFP,VP,RV is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface. Especially the M5M5256DVP,RV are packaged in a 28-pin thin small outline package.Two types of devices are available, M5M5256DVP(normal lead bend type package), M5M5256DRV(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board.
PIN CONFIGURATION (TOP VIEW)
A14 A12 1 2 A7 3 A6 4 A5 5 A4 6 7 A3 A2 8 A1 9 A0 10 DQ1 11 DQ2 12 DQ3 13 GND 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /W A13 A8 A9 A11 /OE A10 /S DQ8 DQ7 DQ6 DQ5 DQ4
M5M5256DFP
FEATURE
Type Access Power supply current time Active Stand-by (max) (max) (max) 70ns 12A M5M5256DFP,VP,RV-85VLL 85ns 25mA
(Vcc=3.6V) (Vcc=3.6V)
Outline 28P2W-C (DFP) 22 /OE 23 A11 24 A9 25 A8 26 A13 27 /W 28Vcc 1 A14 2 A12 3 A7 4 A6 5 A5 6 A4 7 A3 A10 21 /S 20 DQ8 19 DQ7 18 DQ6 17 DQ5 16 DQ415 GND 14 DQ3 13 DQ2 12 DQ1 11 A0 10 A1 9 A2 8
M5M5256DFP,VP,RV-70VLL
M5M5256DFP,VP,RV-70VXL M5M5256DFP,VP,RV-85VXL
70ns 85ns
2.4A
(Vcc=3.6V)
0.05A
(Vcc=3.0V, Typical)
M5M5256DVP
*Single +3.30.3V power supply *No clocks, no refresh *Data-Hold on +2.0V power supply *Directly TTL compatible : all inputs and outputs *Three-state outputs : OR-tie capability */OE prevents data contention in the I/O bus *Common Data I/O *Battery backup capability *Low stand-by current**********0.05A(typ.)
Outline 28P2C-A (DVP)
PACKAGE
M5M5256DFP : 28 pin 450 mil SOP M5M5256DVP,RV : 28pin 8 X 13.4 mm2 TSOP
APPLICATION
Small capacity memory units
7 A3 6 A4 5 A5 4 A6 3 A7 2 A12 1 A14 28 Vcc 27 /W 26 A13 25 A8 24 A9 23 A11 22 /OE
M5M5256DRV
A2 8 A1 9 A0 10 DQ1 11 DQ2 12 DQ3 13 GND 14 DQ4 15 DQ5 16 DQ6 17 DQ7 18 DQ8 19 /S 20 A10 21
Outline 28P2C-B (DRV)
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL,-85VLL, -70VXL,-85VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DP,FP,VP,RV is determined by a combination of the device control inputs /S, /W and /OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with the low level /S. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting /W at a high level and /OE at a low level while /S are in an active state. When setting /S at a high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by /S. The power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
/S H L L L /W X L H H /OE X X L H Mode Non selection Write Read DQ High-impedance DIN DOUT High-impedance Icc Stand-by Active Active Active
BLOCK DIAGRAM
A8 A 13 A 14 A 12 A7 A6 A5 A4 ADDRESS INPUT A3
25 26 ADDRESS INPUT BUFFER ROW DECODER 1 2 2 3 4 5 6 7 32768 WORD SENSE ANPLIFIER OUTPUT BUFFER X 8BIT
11 12 13 15 16 17 18 19
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DATA I/O
(512 ROWS X 512 COLUMNS)
A2 A1 A0 A 10 A 11 A9 WRITE CONTROL INPUT /W CHIP SELECT INPUT /S
8 DATA INPUT BUFFER COLUMN DECODER 9 10 21 23 24 ADDRESS INPUT BUFFER
CLOCK GENERATOR
27 20
28 14
VCC (3.3V) GND (0V)
OUTPUT ENABLE /OE INPUT
22
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL,-85VLL, -70VXL,-85VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Vcc VI VO Pd Topr Tstg Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25C Ratings -0.3*~4.6 -0.3*~Vcc+0.3
(Max 4.6)
Unit V V V mW
C C
0~Vcc 700 0~70 -65~150
* -3.0V in case of AC ( Pulse width 30ns )
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH1 VOH2 VOL II IO Parameter High-level input voltage Low-level input voltage High-level output voltage 1 IOH=-0.5mA
(Ta=0~70C, Vcc=3.30.3V, unless otherwise noted)
Test conditions
Limits Min 2.0 -0.3* 2.4
Vcc -0.5
Typ
Max
Vcc +0.3
Unit V V V V
0.6
High-level output voltage 2 IOH=-0.05mA Low-level output voltage Input current Output current in off-state Active supply current
(AC, MOS level )
IOL=1mA VI=0~Vcc /S=VIH or or /OE=VIH, VI/O=0~Vcc Min. /S0.2V, cycle Other inputs<0.2V or >Vcc-0.2V 1MHz Output-open Min. cycle /S=VIL, other inputs=VIH or VIL Output-open Min. cycle /SVcc-0.2V, other inputs=0~Vcc /S=VIH,other inputs=0~Vcc Min. cycle 1MHz -VLL -VXL 0.05 13 1.5 14 1.5
0.4 1 1 25
V uA uA
Icc1
mA 3 25 mA 3 12 2.4 0.33 uA mA
Icc2
Active supply current
(AC, TTL level )
Icc3 Icc4
Stand-by current Stand-by current
* -3.0V in case of AC ( Pulse width 30ns )
CAPACITANCE
Symbol CI CO
(Ta=0~70C, Vcc=3.30.3V, unless otherwise noted)
Parameter Input capacitance Output capacitance
Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
Min
Limits Typ Max 6 8
Unit pF pF
Note 0: Direction for current flowing into an IC is positive (no mark). 1: Typical value is one at Ta = 25C. 2: CI, CO are periodically sampled and are not 100% tested.
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL,-85VLL, -70VXL,-85VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) MEASUREMENT CONDITIONS
(Ta = 0~70C, Vcc=3.30.3V, unless otherwise noted )
Input pulse level*******************VIH=2.2V,VIL=0.4V Input rise and fall time**********5ns Reference level********************VOH=VOL=1.5V Output loads*************************Fig.1,CL=30pF (-70VLL,-70VXL ) CL=50pF (-85VLL,-85VXL ) CL=5pF (for ten,tdis) Transition is measured 500mV from steady state voltage. (for ten,tdis)
DQ
(Including scope and JIG)
CL
Fig.1 Output load
(2) READ CYCLE
Symbol tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after /S high Output disable time after /OE high Output enable time after /S low Output enable time after /OE low Data valid time after address Limits -70VLL, VXL -85VLL, VXL Min Max Min Max 70 85 70 85 70 85 35 45 25 25 25 25 5 10 5 10 10 10 Unit ns ns ns ns ns ns ns ns ns
(3) WRITE CYCLE
Limits -70VLL, VXL -85VLL, VXL Unit Min Max Min Max ns tCW 70 85 Write cycle time tw(W) ns Write pulse width 55 60 tsu(A) ns Address setup time 0 0 tsu(A-WH) Address setup time with respect to /W high 65 ns 70 tsu(S) ns Chip select setup time 65 70 tsu(D) ns Data setup time 30 35 th(D) ns Data hold time 0 0 trec(W) ns Write recovery time 0 0 tdis(W) ns Output disable time from /W low 25 25 tdis(OE) Output disable time from /OE high ns 25 25 ten(W) ns Output enable time from /W high 5 10 ten(OE) ns Output enable time from /OE low 5 10 Symbol Parameter
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL,-85VLL, -70VXL,-85VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS Read cycle
A0~14 ta(A) ta (S) /S
(Note 3)
tCR
tv (A)
ta (OE) ten (OE)
tdis (S)
(Note 3)
/OE
(Note 3)
tdis (OE) ten (S)
(Note 3)
DQ1~8
/W = "H" level
DATA VALID
Write cycle (/W control mode)
A0~14
tCW
tsu (S) /S
(Note 3) (Note 3)
tsu (A-WH) /OE tsu (A) /W tdis (W) tdis (OE) DQ1~8
(Note 3)
tw (W)
trec (W)
ten (W)
ten(OE)
DATA IN STABLE (Note 3)
tsu (D)
th (D)
MITSUBISHI ELECTRIC
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL,-85VLL, -70VXL,-85VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S control mode)
tCW A0~14 tsu (A) /S
(Note 5)
tsu (S)
trec (W)
/W
(Note 3)
(Note 4)
tsu (D)
th (D)
(Note 3)
DQ1~8
DATA IN STABLE
Note 3 : Hatching indicates the state is "don't care". 4 : Writing is executed in overlap of /S and /W low. 5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state. 6 : Don't apply inverted phase signal externally when DQ pin is output mode. 7 : ten, tdis are periodically sampled and are not 100% tested.
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'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -70VLL,-85VLL, -70VXL,-85VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol
Vcc (PD) VI (/S) Icc (PD)
(Ta = 0~70C, Vcc=3.30.3V, unless otherwise noted)
Parameter
Power down supply voltage Chip select input /S Power down supply current
Test conditions
Min 2 2
-VLL -VXL
Limits Typ Max
Unit
V V
Vcc = 3V,/SVcc-0.2V, Other inputs=0~Vcc
(Note 7)
10 2
uA
0.05
(Note 8)
Note7: ICC (PD) = 1uA in case of Ta = 25C Note8: ICC (PD) = 0.2uA in case of Ta = 25C
(2) TIMING REQUIREMENTS (Ta = 0~70C, Vcc=3.30.3V, unless otherwise noted )
Symbol tsu (PD) trec (PD) Parameter
Power down set up time Power down recovery time
Test conditions
Min
0
Limits Typ Max
Unit
ns ns
tCR
(3) POWER DOWN CHARACTERISTICS /S control mode
Vcc tsu (PD)
2.0V 3.0V 3.0V
trec (PD)
2.0V
/S
/SVcc-0.2V
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